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聯詠96670晶片規格書
由 MK不打烊 發表于 農業2022-12-01
簡介6VFull Speed DC SpecificationsInput Levels (differential receiver)VDIDifferential inputsensitivi ty0
ct4n2cm0是什麼意思
NT96670
2017/11/06 - 1 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal liability or responsibility for the accuracy,
completeness, or usefulness of any such information。
NT96670
Imaging Processor
Preliminary
NT96670
2017/11/06 - 2 - Version 0。3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Ta b l e o f C o n t e n ts
REVISION HISTORY …………………………。。 ………………………………………………………………………………。 4
FEATURES …………………………。。 …………………………………………………………………………………………。。。。 5
GENERAL DESCRIPTI ON …………………………。。 ……………………………………………………………………。。。 11
BLOCK DIAGRAM …………………………。。 ………………………………………………………………………………。。 12
PIN CONFIGURATION
…………………………。。 …………………………………………………………………………。。 13
PIN CONFIGURATION …………………………。。 …………………………………………………………………………。。 14
1。 TFBGA -288 …………………………。。 ……………………………………………………………………………………。。。。。 14
PIN DESCRIPTIONS …………………………。。 …………………………………………………………………………。。。。。 16
2。 NT96670 288 PINS …………………………。。 ………………………………………………………………………………。 17
2。1。 System interface (10) …………………………。。 ………………………………………………………………………………。。。 17
2。2。 RTC & Power Button Controller (9) …………………………。。 …………………………………………………………。。。。。 17
2。3。 DRAM interface (52) …………………………。。 ………………………………………………………………………………。。。。。 18
2。4。 Sensor interface (27) …………………………。。 ………………………………………………………………………………。。。。 19
2。5。 Memory Card interface (26) …………………………。。 ……………………………………………………………………。。。。。 21
2。6。 LCD interface (24) …………………………。。 ……………………………………………………………………………………。。 23
2。7。 PW M and Peripheral I/O (28) ………………………………………………………………………………………………。。。。。 24
2。8。 Dedicated I/O (2) …………………………。。 ……………………………………………………………………………………。。。。。 26
2。9。 ADC interface (4) …………………………。。 ……………………………………………………………………………………。。。。 26
2。10。 Audio Codec(9) …………………………。。 …………………………………………………………………………………………。 26
2。11。 TV interface ( 1) …………………………。。 …………………………………………………………………………………………。 27
2。12。 Ethernet interface (4) …………………………。。 ………………………………………………………………………………。。。。 27
2。13。 USB device interface (3) …………………………。。 …………………………………………………………………………。。。。 27
2。14。 Power (127) …………………………。。 ………………………………………………………………………………………………。 27
PAC K AG E INFORMATION …………………………。。 ……………………………………………………………………。 29
3。 TFBGA -288 …………………………。。 ……………………………………………………………………………………。。。。。 29
ELECTRICAL CHARACTER ISTICS …………………………。。 ……………………………………………………。。。。。 30
NT96670
2017/11/06 - 3 - Version 0。3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
4。 ABSOLUTE MAXIMUM RAT IN G S …………………………。。 ………………………………………………………………。。。。 30
5。 ESD PERFORMANCE …………………………。。 ……………………………………………………………………………… 31
6。 LAT C H -UP IMMUNITY …………………………。。 ……………………………………………………………………………… 31
7。 RECOMMENDED OPERATING CONDITIONS …………………………。。 …………………………………………………… 31
8。 AC/DC C HARACTERISTICS …………………………。。 ……………………………………………………………………。。。 32
8。1。 Power on Sequence …………………………。。 ………………………………………………………………………………。。。。。 32
8。2。 General I/O …………………………。。 ………………………………………………………………………………………………。。 35
8。3。 Specif i c f uncti on I /O (RT C, Reset, LVD and PBC) …………………………。。 ………………………………………… 38
8。4。 DDR3 / DDR3L Interfance …………………………。。 …………………………………………………………………………。。 39
8。5。 High speed serial interface(MIPI CSI, LVDS, HiSPi) ………………………………………………………………。。。。 41
8。6。 High speed serial interface(SLVS -EC) …………………………。。 ………………………………………………………… 43
8。7。 ADC …………………………。。 …………………………………………………………………………………………………………。 45
8。8。 Audio Codec …………………………。。 ……………………………………………………………………………………………… 45
8。9。 TV encoder …………………………。。 ………………………………………………………………………………………………。。 46
8。10。 USB 2。0(High -Speed/ F ul l -Speed) …………………………。。 ………………………………………………………………。。 46
8。11。 USB Charging Port Detect …………………………。。 …………………………………………………………………………。 50
IMPORTANT NOTICE …………………………。。 …………………………………………………………………………。。。 51
NT96670
2017/11/06 - 4 - Version 0。3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Revision History
Rev。 Date Author Contents
V0。1 201 7/07 /25
Kevin Hung draft
V0。2 2017/09/25
Kevin Hung Modify electrical specification / H SI pin mux table
V0。3 2017/ 11/06
Kevin Hung Modify part number and electrical specification
NT96670
2017/11/06 - 5 - Version 0。3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Features
High Performance 32-bit CPU
Dual MIPS32 24Kec with ASE DSP extension
MMU embedded
CPU1 with 16KB instruction and 16KB data cache
CPU2 with 32KB instruction and 32KB data cache
CPU operating frequency up to 640MHz
Embedded ICE makes firmware debugging easier
High Performance CEVA MM3101 Image/Video DSP ( embedded DSP version only )
540 MHz CEVA DSP
Power M anagement features
Firmware configurable operating freq uency of each functional block to meet best power budget
Internal power domain partition
Integrated Clock Generator
Internal PLL with spread spectrum capability
12MHz system
32768Hz RTC oscillator
Scalable Memory Bus Architecture
16-bit DDR3/3L/2L SDRAM bu s, supporting up to 8Gb
DRAM operating data rate up to DDR3 -160 0, DDR3L -1400 or DDR2L -1066 without ODT
Sensor Interface Engine
Support high speed serial interface like MIPI(1。5G)/ sub -LV DS / HiS P i (1 G ) u p t o 4 c ha nn e l s a nd 2
clocks for most commercial CMOS s ensors including Sony, Panasonic, Aptina, Samsung, Sharp
and Omnivision, etc。 2 clock channels allow dual two data lanes sensors application usage。
Support parallel sensor interface for most commercial CMOS sensors including Aptina and
Omnivision
Support max。 1 BT。601/656(8 -bit)/BT。1120 video input
Support 8-/10 -/12 -bit sensor data input
Support burst shot up to 30fps for 5MP sensor
Support parallel interface sensor pixel clock up to 120MHz
Support RGBIR 4x4
Support HDR sensor composition such as SONY DOL m ode and Omnivision staggered mode
Built-in color pattern generation
NT96670
2017/11/06 - 6 - Version 0。3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Sensor black level clamping
Efficient defect concealment algorithm
Raw image scale down for video & high ISO image
Flexible image analysis flow for AE, AWB and AF purpose
Programmable hist ogram analysis
R/G/B Gamma LU T for sensor linearization correction
Image Processing Engine
In-pipeline l ens shading compensation technology
In-pipeline color shading compensation technology
Support in-frame dark frame subtraction with smart defect detectio n algorithm
Support EIS with gyro -sensor input
Mechanical shutter control
Flash light control
Advanced image pipeline architecture for multi -purpose hardware acceleration
Proprietary advanced anti -alias Bayer CFA color interpolation
Advanced edge rendering control and continuity enhancement
Powerful noise reduction technology for still and video recording
Support advanced motion compensated temporal filtering (MCTF) for efficient video noise reduction
Support temporal noise reduction with ghost reduction
R/G/B Gamma LUT
High precision color correction matrix for sRGB or specific color requirement
Brightness/contrast and hue/saturation adjustment
Specif ic color control technology ( Patent ed)
False color suppression
Anti-fog function
Wide dynamic range (WDR) fo r global/local illumination enhancement
Image Manipulation Engine
High quality scaling engine for seamless digital zooming from 1/16x to 16x
Support thumbnail image generation
Forward/inverse color space transform
Face Detection Engine
Ve r y h i gh sp ee d f ac e detection and tracking
High accuracy under different light source
NT96670
2017/11/06 - 7 - Version 0。3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Programmable target data bas e
Digital Image S tabilizer
Remove unintended hand movement from an image sequence
Single frame compensation for video (Total compensation)
Accumulate frame compe nsation for video (Smart compensation)
Programmable total compensation range
LCD/TV Display
High performance scaling up/down engine, programmable gamma correction , color transform and
color management for LCD or TV display
Separate OSD for LCD panel and TV
Support digital LCD interface for AUO , Casio, CMI (all digital panels will be supported)
Support 90rotation/flip/mirror
Support PAL / NTSC video encoder (CVBS format) with automatic load detection
Integrated 1 internal 10 -bit video DACs
Support digital interface BT。601/656/1120 output port
3。3V / 1。8V LCD / Digital video out
Graphic Engine
Copy and paste
Geometric operation including mirror, flip and rotation
Arithmetic operation including addition, subtraction, color keying, logic operation and alpha
blending
Cipher
64-bit DES, 3DES support
Supports 3-key and 2 -key modes for the 3DES algorithm
AES-128 and AES -256
Supports the operating modes of counter with Cipher Block Chaining -Message Authentication
Code (CCM), Galois/Counter Mode (GCM), electronic code book (ECB), cipher block chaining
(CBC), cipher feedback (CFB), output feedback (OFB), and counter (CTR) for the
DES/3DES/ AES algorithm
Support multi-channel encryption and decryption
Hash
Support SHA1,SHA256,HMAC -SHA1,HMAC -SHA256 algorithm
RSA
Support 512-bit, 1024 -bit, 2048 -bit , 4096 -bit key
NT96670
2017/11/06 - 8 - Version 0。3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Support Key checksum by CRC32
True Random Number Generator
Generate true random number
32-bit s Random number generator
Video C ODEC
Support H。264/AVC codec BP/MP /HP, level 5。1
Support H。265/HEVC codec MP, level 5。0
Support real-time capability for 5 -megapixel@30fps +720p@30fps + WVGA@30fps
Support frame rotation 90 degree counterclockwise and clockwise
Support configurable GOP
Support ROI (10 sets) enhancing picture quality
Support CBR, VBR and Macro block QP table
Support OSD function
Support Scalable Video Codec (SVC -T)
Support video format MP4, AVI, MOV
Support full frame still capture while video recording
F/W Audio CODEC
AAC encode / decode (32KHz, 48KHz @ 192kbps)
ADPCM /G。711 / G。726
AEC / ANR and ALC
H/W Audio CODEC
stereo 16 -bits ADC audio recording
stereo 16-bits DAC audio playback
Programmable ALC / Noise Gate l
Audio sampling rate : 8k, 11。025k, 12k, 16k, 22。05k, 24k, 32k, 44。1k, 48kHz
Support dual microphone inputs
JPEG CODEC
Supports Motion JPEG 30fps @1080P30 video clip/playback function
Max。 pixel clock 240Mpixel / sec
Support ISO/IEC 10918 -1 baseline J PEG compression/decompression。
Still image maximum resolutions will be up to 65536x65536 pixels
Support input format: 422, 420, 411, 400, 211
JPEG supports d ownloadable Quantization and Huffman tables
Support Exchangeable Image File format (EXIF 2。2。3 and newer)
NT96670
2017/11/06 - 9 - Version 0。3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Support MPO file format for 3D image
Digital Audio Interface
Support I2S codec interface
Audio clock generator
Dual Graphic -based OSD
Support 8-bit palette and ARGB(8565 or 8888) OSD architecture
256 colors simultaneously out of true color at 8-bit palette OSD
Programmable width & height to meet LCD/TV‘s resolution exactly
Picture in picture function
Support Codec video encode OSD function
8 sets privacy mask
Support 4 sets data stamp
Storage Memory Controller
Secure Digital card and SDIO
Support SD 3。0
Support UHS -I: UHS50, UHS104 (Max。 freq。 96MHz)
Support SPI-NAND and SPI -NOR flash
Support eMMC v5。0 interface
USB
Fully compliant with USB2。0 device/host (1 set)
Support Control / Isochronous / Interrupt and Bulk transfer
Support PC camera mode
Timer s
RTC can be powered by separate backup battery and operating f rom 1。 5V to 3。3 V
Watch dog timer
20 programmable HW timers support resolution up to 3MHz and 32 bits counter
Peripheral Interface
Support I2C interface
Support 16 channels PW M including built -in 4 ( 3 sets) pattern generators for -Stepping motor
control
Support GPIO and flexible PWM interface with micro -stepping
Support programmable 3 -wired serial interface
Support SPI interface
Dedicated SPI for gyroscope reading
NT96670
2017/11/06 - 10 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Support NFC & BLE4。0 interface
Support UART interface
Support Remote interface
Support 4 channels of 10 -bit ADC, the max。 sample rate up to 12。5 KHz per channel
Embed Ethernet 10M/100M MAC and support RMII/MII/RevMII interface。 PHY clock output and
TSO/UFO acceleration。
Embedded Ethernet PHY, Fully compliant with 100BASE -TX, and 10BASE -T PMD level
standards (IEEE 802。3, 802。3u)
On -chip Boot Strap Loader
Built-in on -chip mask ROM
User program can be stored in NAND -type flash and external static memory is not necessary
On-chip mask ROM ca n be disabled
System can boot from SPI NOR/ NAND flash, memory card s, eMMC, Ethernet
Quadruple V oltage Power Supply
0。9V core logic voltage
1。5V DDR3, 1。35V DDR3L or 1。5V DDR2L SDRAM interface voltage
2。5V analog circuit voltage
3。3V I/O interface and anal og circuit voltage
Package
NT96670BG: 288ball TFBGA, 12x12 mm^2
NT96670
2017/11/06 - 11 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
General Description
NT96670 is a highly -integrated SoC targets on 2M ~5M profession IP camera system。 It builds in
MIPS32 24KEc dual cores CPU, video input, ISP, H。264/H265 encoder, JPEG encoder, intelligent
video analysis functions, graphic engine, display controller, encryption engine, ethernet PHY, USB 2。0
Host/Device, RTC and SD/SDIO 3。0 reduce the ov erall system cost。
NT96670
2017/11/06 - 12 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Block Diagram
PC / NVRNT 96670
LCD
TV
SD / eMMC StorageRTC &
Power control
Fla sh Light /
I
2C or SIF
GPIO / ADC
GDC / FD
DIS /Motion
SDIO
Controller USB 2。
0
Host/Device
UART
Sensor IF 1
(CSI /
sLVD S)
Sensor IF 2
(CSI /
sLVD S)
LCD
controller
10/
100
Ethernet PHY
PWM
( u - st ep)
Timer/WDT
TV Encoder
Audio C odec
/ I2 S interfa ce
Fla sh
Controller SDRAM
Controller Memory Card
ControllerImage
Processor 3 DNR /
Anti-
fog
OSD /
Graphics
Dual CPU
MIPS 24 Kec
JPEG
Engine
H。264 /H 。
265
Vi deo Codec
32。
768 K
12
M Key /
Battery detect
Motor Driver Lens & Sensor
Cipher
AMP DDR IIIDRAM
CEVA DSP(
option)
NT96670
2017/11/06 - 13 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Pin Configuration
NT96670
2017/11/06 - 14 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Pin Configuration
1。
TFBGA -288
Pin Pin Name
Pin Pin Name
Pin Pin Name
Pin Pin Name
Pin Pin Name
A1 DR_D14 D5 P_GPIO24 H6 GND L17 MC13 R17 LCD4
A2 DR_D12 D6 P_GPIO22 H7 VDD_DRDIO
L18 MC16 R18 LCD3
A3 P_GPIO21 D7 P_GPIO16 H8 GND M1 DR_CLK# T1 DR_A5
A4 P_GPIO20 D8 P_GPIO13 H9 GND M2 DR_CLK T2 DR_A9
A5 P_GPIO15 D9 S_GPIO14 H10 GND M3 GND T3 DR_A12
A6 UART_TX D10 S_GPIO11 H11 VDDC_K M4 DR_ODT T4 DR_RESET#
A7 MC8 D11 S_GPIO9 H12 VDDC_K M6 DR_ZQ T5 PWR_EN
A8 MC6 D12 S_GPIO12 H13 VDDC_K M7 AV D D_ MP L L T6 PWR_SW4
A9 MC5 D13 AGND_HSI H15 P_GPIO2 M8 VDDL_MPLL T7 PWR_EN3
A10 MC1 D14 S_GPIO8 H16 P_GPIO11 M9 GND T8 DGPIO1
A11 HSI_D3P D15 SN_PXCLK H17 P_GPIO4 M10 AV D D_ A D C T9 JTAG_TDO
A12 HSI_D2P D16 SN_MCLK H18 P_GPIO7 M11 VDDC_K T10 GND_ETH
A13 HSI_CK1P D17 SN_VD J1 DR_DQS0# M12 VCC_SDLI T11 GND_ETH
A14 HSI_CK0P D18 LN_R J2 DR_DQS0 M13 SD_CAP2 T12 AD_IN0
A15 HSI_D0P E1 DR_D8 J3 VDD_BGDR M15 MC18 T13 AGND_USB
A16 HSI_D1P E2 GND J4 GND M16 MC23 T14 AD_IN2
A17 MIC_L_INN E3 DR_D10 J6 VDD_DRPIO M17 MC19 T15 LCD10
A18 MIC_L_INP E4 GND J7 GND M18 MC12 T16 LCD9
B1 DR_D13 E15 AV C C_ A U D J8 GND N1 DR_CAS# T17 LCD8
B2 GND E16 TP1 J9 GND N2 DR_RAS# T18 LCD6
B3 DR_D15 E17 AUD_VMIDX J10 GND
N3 DR_CKE U1 DR_A1
B4 P_GPIO17 E18 LN_L J11 GND N4 DR_A3 U2 DR_A4
B5 P_GPIO14 F1 DR_DM0 J12 VDDC_K N6 VCC_RTC U3 DR_A11
B6 UART_RX F2 DR_DM1 J13 AGND_TV N7 GND_MPLL U4 DR_RST#
B7 MC10 F3 GND J15 P_GPIO1 N8 VCC_VBAT U5 PWR_SW3
B8 MC7 F4 GND J16 P_GPIO0
N9 VCC_GIO U6 XTAL_SYSI
B9 MC4 F6 VCC_GIO J17 P_GPIO5 N10 VCC_ETH U7 PWR_EN2
B10 MC2 F7 VCC_GIO J18 P_GPIO6 N11 AV C C_ U S B U8 XTAL_RTCI
B11 HSI_D3N F8 VDDC_K K1 DR_D7 N12 VDDM_LCD U9 DGPIO0
B12 HSI_D2N F9 VDDM_MC K2 DR_D5 N13 VDDM_LCD U10 ETH_TP
B13 HSI_CK1N F10 VDDM_SN K3 VDD_DRCLK N15 LCD1 U11 ETH_RP
B14 HSI_CK0N F11 VDDM_HSIO K4 GND N16 LCD0 U12 RESET#
B15 HSI_D0N F12 AV D D C_ H S IK K6 VDDC_DRK N17 MC21 U13 USB_DM
B16 HSI_D1N F13 VDD_HSIRX K7 VDDC_K N18 MC20 U14 LCD21
B17 MIC_R_INN F15 AUD_CAP K8 VDDC_K
P1 DR_A10 U15 LCD19
B18 MIC_R_INP F16 AGND_AUD K9 GND P2 DR_WE# U16 LCD14
C1 DR_DQS1 F17 P_GPIO12 K10 GND P3 DR_BA0 U17 LCD13
C2 DR_DQS1# F18 P_GPIO10 K11 GND P4 DR_BA2 U18 LCD11
NT96670
2017/11/06 - 15 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
C3 GND G1 DR_D2 K12 VDDC_K P15 LCD22 V1 DR_A6
C4 P_GPIO23 G2 DR_D0 K13 AV D D_ T V P16 LCD17 V2 DR_A8
C5 P_GPIO18 G3 GND K15 P_GPIO3 P17 LCD12 V3 DR_A13
C6 P_GPIO19 G4 GND K16 MC17 P18 LCD2 V4 DR_A14
C7 MC11 G6 VDDL_DR K17 MC15 R1 DR_A0 V5 PWR_SW2
C8 MC9 G7 VDD_DRDIO K18 TV_CVBS R2 DR_A2 V6 XTAL_SYSO
C9 MC3 G8 VDDC_K L1 DR_D4 R3 DR_BA1 V7 PWR_SW1
C10 MC0 G9 VDDC_K L2 GND R4 DR_A7 V8 XTAL_RTCO
C11 S_GPIO13 G10 VDDC_K L3 DR_D6 R5 DR_A15 V9 JTAG_TMS
C12 SN_HD G11 VDDC_K L4 DR_CS# R6 TESTEN V10 ETH_TN
C13 S_GPIO10 G12 VDDC_K L6 VDD_DRCIO R7 TP3 V11 ETH_RN
C14 S_GPIO7 G13
VDDC_K L7 VDD_DRCIO R8 JTAG_TCK V12 SYS_RSTOUT#
C15 S_GPIO6 G15 AGND_AUD L8 VDDC_K R9 JTAG_TDI V13 USB_DP
C16 S_GPIO5 G16 VDDM_PIO L9 GND R10 JTAG_TRST V14 LCD23
C17 S_GPIO4 G17 P_GPIO9 L10 AGND_ADC R11 VBUS V15 LCD20
C18 MIC_BIAS G18 P_GPIO8 L11 VDDC_K
R12 AD_IN1 V16 LCD18
D1 DR_D11 H1 DR_D1 L12 VDDC_K R13 AD_IN3 V17 LCD16
D2 DR_D9 H2 GND L13 SD_CAP R14 TP2 V18 LCD15
D3 GND H3 DR_D3 L15 MC22 R15 LCD7
D4 P_GPIO25 H4 GND L16 MC14 R16 LCD5
NT96670
2017/11/06 - 16 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Pin Descriptions
I = input port with Schmitt trigger
O = output port with normal driving/sinking
I/O = bi -directional port with normal driving/sinking and Schmitt input
I/OD = bi -directional port with open drain output and Schmitt input
mv I/O = multi voltage bi -direction port with Schmitt input
I/O
5VT = bi -dir ectional port with normal driving/sinking and 5V tolerance input
I/O
A / B / C / D / E / S D = bi -direction port with different driving/sinking capability
HSI = high speed serial interface with multi voltage input port
LV D = l o w v o l tag e de te c t f u nc t i on p in
p/u = internal pull -up
p/d = internal pull -down
AI = analog input port
AO = analog output port
AI/O = analog bi -directional port
H = output high
L = output low
P = power or ground
Note: * means this pin has interrupted function。
NT96670
2017/11/06 - 17 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
2。
NT96670 288 pins
T otal:280 pins
2。1。
System interface (10)
Pin No。
Name
Ty p e Reset Descriptions
U6 XTAL_SYSI AI - Crystal input for s ystem oscillator。 (12MHz)
V6 XTAL_SYSO AO - Output for system oscillator 。
U12 RESET# LV D p/u System Reset
。 Connect a capacitor to ground for re
set
time control。
V12 SYS_RSTO# O
E O Reset signal output for peripheral。
R6 TESTEN I I p/d
Te s t m o d e e n a b l e 。 K e e p l o w f o r n o r m a l o p e r a t i o n 。
R10 JTAG_TRST
/
DGPI
O2* /
BS0 I/O
A I p/d
CPU ’ s JTAG test interface / BS2。。0 : BOOT_SRC
Note: BOOT_SRC BS3 pin is LCD
The boot source setting description:
0x0: SPI (NOR)
0x1: SDIO
0x2: SPI_NAND with on die ECC(2 kbytes)
0x3: SPI_NAND with RS ECC(2 kbytes)
0x4: ETHERNET
0x5: USB high speed
0x6: SPI_NAND with on die ECC(4 kbytes)
0x7: BMC (SPI)
0x8: eMMC(4 bits data bus)
0x9: eMMC(8 bits data bus)
0xA: SPI_NAND with RS ECC(4 kbytes)
0xB: USB full speed
Others: Reserved
V9 JTAG_TMS
/
DGPI
O3* /
BS1 I/O
A I p/d
R8 JTAG_TCK
/
DGPI
O4* /
BS2 I/O
A I p/d
R9 JTAG_TDI
/
DGPI
O5* /
BS5 I/O
A I p/d
EJTAG data input/BS5 : EJTAG_SEL
EJTAG select
0: GPIO (TRST, TMS, TCK, TDI, TDO are GPIO)
1: EJTAG (assign DGPIO2~DGPIO6 to JTAG on boot)
T9 JTAG_TDO
/
DGPI
O6* /
BS12 I/O
A I p/d
EJTAG data output/BS12 : WDT_FAIL_RESET_FUNC
Enable WDT fail reset function。 Enable this function can
skip internal storage when internal storage boot failed。
(boot from SPI nand/SPI nor /eMMC)
0: Enable
1: Disable
2。2。
RTC & Power Button Controller ( 9)
Pin No。
Name
Ty p e Default Descriptions
U8 XTAL_RTCI AI - Crystal input for real time clock oscillator。 (32。768KHz)。
V8 XTAL_RTCO AO - Output for real time clock oscillator。
V7 PWR_SW1* AI I p/d
Power on/off signal input。 (ON/OFF switch use)
V5 PWR_SW2*# AI I p/u
Power on/off signal input。 (falling edge trigger)
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
U5 PWR_SW3 AI I p/d
Power on/off signal input。
T6 PWR_SW4 AI I p/d
Power on/off signal input。 (Bettery in use)
T5 PWR_EN AO - Power enable signal output。
U7 PWR_EN2 AO - Power enable signal output。
T7 PWR_EN3 AO - Power enable signal output。
Note*: PW R_SW can trigger interrupt (share RTC in terrupt)。
Note: If those PWR_SW pins aren ’t used, Novatek recommends each PWR_SW connect to default
level by a resistor。
2。3。
DRAM interface (52 )
Pin No。
Name
Ty p e Reset Descriptions
T4 DR_RESET# O - Reset signal output of DDR PHY
U4 DR_RST# O - Reset signa l open drain output for Suspend mode
L4 DR_CS# O - DRAM chip select
M4 DR_ODT O - DRAM on die terminator control
M6 DR_ZQ AI - DRAM reference pin for ZQ calibration
M2 DR_CLK O -
DRAM differential c lock output。
M1 DR_CLK# O -
N3 DR_CKE O - DRAM cloc k enable 。
N1 DR_CAS#
O - DRAM control signals
N2 DR_RAS#
P2 DR_WE#
P3 DR_BA0
O - DRAM b ank select。
R3 DR_BA1
P4 DR_BA2
R1 DR_A0
O - DRAM address bus。
U1 DR_A1
R2 DR_A2
N4 DR_A3
U2 DR_A4
T1 DR_A5
V1 DR_A6
R4 DR_A7
V2 DR_A8
T2 DR_A9
P1 DR_A10
U3 DR_A11
T3 DR_A12
V3 DR_A13
V4 DR_A14
R5 DR_A1 5
F1 DR_DQM0
O - DRAM
data mask : DQM 0 corresponds to DQ0 -
DQ7 and
DQM1 corresponds to DQ8 -DQ15。
F2 DR_DQM1
J2 DR_DQS0
I/O - DRAM data strob
e。 DQS0 corresponds to DQ0 -
DQ7 and
DQS1 corresponds to DQ8 -DQ15。
J1 DR_DQS0#
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
C1 DR_DQS1
C2 DR_DQS1#
G2 DR_D0
I/O - DRAM d
ata bus input/output, lower byte。
(Each bits of lower byte may be
permute d to make
routing simpler)。 H1 DR_D1
G1 DR_D2
H3 DR_D3
L1 DR_D4
K2 DR_D5
L3 DR_D6
K1 DR_D7
E1 DR_D8
I/O - DRAM d
ata bus input/output, upper byte。
(Each bits of upper byte may be
permute d to make
routing simpler) D2 DR_D9
E3 DR_D10
D1 DR_D11
A2 DR_D12
B1 DR_D13
A1 DR_D14
B3 DR_D15
2。4。
Sensor interface (27)
Pin No。
Name
Ty p e
Reset Descriptions
B15 HSI_D0 N
/
HSI_GPI0
HSI
I p/d
High speed differential sensor interface and parallel
interface。
(W hen sensor interf ace is conf igured as high speed
differenti al sensor interface, the clock lane should be a
dedicated differential lane。
And each data lanes may be
permuted in established
group, refer to below table) A15 HSI_D0P
/
HSI _GPI1
B16 HSI_D1N
/
HSI _GPI2
A16 HSI_D1P
/
HSI _GPI3
B14 HSI_CK0N
/
HSI _GPI4
A14 HSI_CK0P
/
HSI _GPI5
B12 HSI_D2N
/
HSI _GPI6
A12 HSI_D2P
/
HSI _GPI7
B11 HSI_D3N
/
HSI _GPI8
A11 HSI_D3P
/
HSI _GPI9
B13 HSI_CK1N
/
HSI _GPI10
A13 HSI_CK1P
/
HSI _GPI11
D16 SN_MCLK
/ mvI/O
A I p/d
Programmable Clock output for sensor
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2017/11/06 - 20 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
S_GPIO [0]
D15 SN_PXCLK /
SN2_MCLK
/
S_GPIO [1] mv
I/O
A I p/d Sensor Pixel Clock Input
Programmable Clock output for sensor 2
D17 SN_VD /
S_GPIO [2] mv
I/O
B I p/d Sensor Ve r t i c a l S y n c input / output
C12 SN_HD /
S_GPIO [3] mv
I/O
B I p/d Sensor Horizontal Sync input / output
C17 SN2_VD /
S_GPIO [4] mv
I/O
B I p/d
Sensor 2 Ve r t i ca l S yn c input / output
C16 SN2_HD /
S_GPIO [5] mv
I/O
B I p/d
Sensor 2 Horizontal Sync input / output
C15 SN_CS /
S_GPIO [6] mv
I/O
B I p/u
General serial interface 0 Chip Select
C14 SN_SCK /
I2C_SCL /
S_GPIO [7] mv
I/O
B I p/u
General serial interface 0 clock output。
I2C -BUS clock output(Open Drain IO structure)
D14 SN_DAT /
I2C_SDA /
S_GPIO [8] mv
I/OD
B I p/u
General serial interface 0 data output。
I2C -BUS data input / output(Open Drain IO structure)
D11 SN2_CS /
S_GPIO [9]* mv
I/OD
B I p/u
General serial interface 2 Chip Select
C13 SN2_SCK /
I2C2_SCL /
S_GPIO [10] mv
I/OD
B I p/u
General serial interface 0 clock output。
I2C -BUS channel 2 clock output(Open Drain IO
structure)
D10 SN2_DAT /
I2C2_SDA /
S_GPIO [11] mv
I/OD
B I p/u
General serial interface 0 data output。
I2C -BUS channel 2 data input / output(Open Drain IO
structure)
D12 SN_SHUT /
S_GPIO [12] mv
I/O
B I p/d
Shutter signal input from sensor
C11 SN_SHUT2 /
S_GPIO [13]* mv
I/O
B I p/d
Shutter signal input from sensor 2
D9 SN_FLASH /
S_GPIO [14] mv
I/O
B I p/d
Flash Signal input from sensor
Note*: The pin can trigger interrupt。
Note1 : The input voltage of HSI_GPI corresponds to VDD M_HSIO 。
Note2 : The mvI/O voltage of Sensor interface corresponds to VDD M_SN 。
Name
MIPI/LVDS/HiSPi
(1C4D)
MIPI / HiSPi
SIE1 & 2 (1C2Dx2) Parallel
SIE1 (RAW 12)
CCIR601
SIE1 (8 bits)
SPI
HSI _GPI[0] HSI_D0 N I
HSI_D0N I
SN_D2 I
HSI _GPI[1] HSI_D0 P I
HSI_D0P I
SN_D3 I
HSI _GPI[2] HSI_D 1N I
HSI_D1N I
SN_D4 I
SN_YC0 I
HSI _GPI[3] HSI_D 1P I
HSI_D1P I
SN_D5 I
SN_YC1 I
HSI _GPI[4] HS I_ CK0N I
HS I_CK0N I
SN_D6 I
SN_YC2 I
HSI _GPI[5] HS I_ CK0P I
HS I_CK0P I
SN_D7 I
SN_YC3 I
HSI _GPI[6] HSI_D 2N I
HSI2_D0N I
SN_D8 I
SN_YC4 I
HSI _GPI[7] HSI_D 2P I
HSI2_D0P I
SN_D9 I
SN_YC5 I
HSI _GPI[8] HSI_D 3N I
HSI2_D 1N I
SN_D10 I
SN_YC6 I
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
HSI _GPI[9] HSI_D 3P I
HSI2_D 1P I
SN_D11(MSB) I SN_YC7 I
HSI _GPI[10] HS I2_CK0N I
SN_D0 I
HSI _GPI[11] HS I2_CK0P I
SN_D1(LSB)
I
S_GPIO[0] SN_MCLK O
SN_MCLK O
SN_MCLK O
SN_MCLK O
S_GPIO[1] SN_PXCLK I
SN2_MCLK I
SN_PXCLK I
SN_PXCLK I
S_GPIO[2] SN_VD I
SN_VD I
SN_VD I/O
SN_VD I
S_GPIO[3] SN_HD I
SN_HD I
SN_HD I/O
SN_HD I
S_GPIO[4]
SN2_VD I/O
SN_FIELD I
S_GPIO[5]
SN2_HD I/O
2。5。
Memory Card interf ace ( 26)
Pin No。
Name
Ty p e
Reset Descriptions
L13 SD_CAP P -
Internal Supply Voltage decoupling for SDIO1 interface。
(3。3/1。8V switchable, default 3。3V)
M13 SD_CAP2 P - Internal Supply Vol
tage decoupling for SDIO2 interface。
(3。3/1。8V switchable, default 3。3V)
C10 MC0 /
C_GPIO[0] mvI/O
B I p/u
Memory Card interface(see below table)
A10 MC1 /
C_GPIO[1] mvI/O
B I p/u
B10 MC2 /
C_GPIO[2] mvI/O
A I p/u
C9 MC3 /
C_GPIO[3]* mvI/O
B I p/u
B9 M C4 /
C_GPIO[4] mvI/O
B I p/u
A9 MC5 /
C_GPIO[5]* mvI/O
B I p/u
A8 MC6 /
C_GPIO[6] mvI/O
B I p/u
B8 MC7 /
C_GPIO[7]* mvI/O
B I p/u
A7 MC8 /
C_GPIO[8] mvI/O
A I p/d
C8 MC9 /
C_GPIO[9]* mvI/O
B I p/u
B7 MC10 /
C_GPIO[10] mvI/O
B I p/u
C7 MC11 /
C_GPIO[11 ] mvI/O
B I p/u
M18 MC12 /
C_GPIO[12]* I/O
SD I p/d
L17 MC13 /
C_GPIO[13] I/O
SD I p/u
L16 MC14 /
C_GPIO[14]* I/O
SD I p/u
K17 MC15 /
C_GPIO[15] I/O
SD I p/u
L18 MC16 / I/O
SD I p/u
NT96670
2017/11/06 - 22 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
C_GPIO[16]
K16 MC17 /
C_GPIO[17]* I/O
SD I p/u
M15 MC18 /
C_GPIO[18] I/O
SD I p/d
Memory Card interface(see below table)
M17 MC19 /
C_GPIO[19] I/O
SD I p/u
N18 MC20 /
C_GPIO[20] I/O
SD I p/u
N17 MC21 /
C_GPIO[21]* I/O
SD I p/u
L15 MC22 /
C_GPIO[22]* I/O
SD I p/u
M16 MC23 /
C_GPIO[23]* I/O
SD I p/u
Note*: The pin ca n trigger interrupt。
Note1: The mvI/O voltage of MC0~11 corresponds to VDD M_MC 。
Note2: The I/O
SD voltage of MC12~17 corresponds to SD_CAP, it could be switched between 3。3/1。8V
by the register。
Note3: The I/O
SD voltage of MC18~23 corresponds to SD_CAP2, it could be switched between
3。3/1。8V by the register。
Memory card interface pinmux table
Name
SD/MMC/eMMC
(BS*)
SPI flash(1~4 bits)
(BS*)
MC0 eMMC_D0 I/O
SPI_DO/D0 I/O
MC1 eMMC_D1 I/O
SPI_DI/D1 I/O
MC2 eMMC_D2 I/O
SPI_W P/D2 I/O
MC3 eMMC_D3 I/O
SPI_HOLD/D3 I/O
MC4 eMMC_D4 I/O
MC5 eMMC_D5 I/O
MC6 eMMC_D6 I/O
MC7 eMMC_D7 I/O
MC8 eMMC_CLK O
SPI_CLK O
MC9 eMMC_STB I
MC10 eMMC_CMD I/O
MC11
SPI_CS# O
Name
SD Card
(BS*)
MC12
SD_CLK O
MC13
SD_CMD I/O
MC14
SD_D0 I/O
MC15
SD_D1 I/O
MC16
SD_D2 I/O
MC17
SD_D3 I/O
Name
SDIO
MC18
SDIO2_CLK O
MC19
SDIO2_CM D I/O
MC20
SDIO2_D0 I/O
MC21
SDIO2_D1 I/O
MC22
SDIO2_D2 I/O
MC23
SDIO2_D3 I/O
NT96670
2017/11/06 - 23 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Note BS*: In general, it is a resident device。 Please choose one of them as boot source(FW)。
2。6。
LCD interface (24)
Pin No。
Name
Ty pe
Reset Descriptions
N16 LCD0 /
L_GPIO[0] mvI/O
B I p/d
LCD Signal Bus
N15 LCD1 /
L_GPIO[1] mvI/O
B I p/d
P18 LCD2 /
L_GPIO[2] mvI/O
B I p/d
R18 LCD3 /
L_GPIO[3] /
BS3 mvI/O
B
I p/d LCD Signal Bus / BS3 : BOOT_SRC
The boot source setting table is shown in JTAG interface。
R17 LCD4 /
L_GPIO[4] mvI/O
B I p/d LCD Signal Bus
R16 LCD5 /
L_GPIO[5] /
BS6 mvI/O
B I p/d LCD Signal Bus / BS6 : PLL_CLK_SEL
Select clock source of PLL (debug only)
0: MPLL clock output
1: From external clock (P_GPIO24)
T18 LCD6 /
L_GPIO[6] mvI/O
B I p/d
LCD Signal Bus
R15 LCD7 /
L_GPIO[7] mvI/O
B I p/d
T17 LCD8 /
L_GPIO[8] mvI/O
A I p/d
T16 LCD9 /
L_GPIO[9] mvI/O
B I p/d
T15 LCD10 /
L_GPIO[10] mvI/O
B I p/d
U18 LCD11 /
L_GPIO[11] mvI/O
B I p/d
P17 LCD12 /
L_GPIO[12] mvI/O
B I p/d
U17 LCD13 /
L_GPIO[13] mvI/O
B I p/d
U16 LCD14 /
L_GPIO[14]* mvI/O
B I p/d
V18 LCD15/
L_GPIO[15]* mvI/O
B I p/d
V17 LCD16 /
L_GPIO[16] mvI/O
B I p/d
P16 LCD17 /
L_GPIO[17] mvI/O
B I p/d
V16 LCD18 /
L_GPIO[18]* mvI/O
A I p/d
U15 LCD19 / mvI/O
B I p/d LCD Signal Bus / BS9。。8 : ETH_MODE_SEL
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
L_GPIO[19] /
BS8 (Only referred by f/w)
0x0: Embeded PHY
0x1: MII
0x2: RMII
0x3: Reserved
V15 LCD20 /
L_GPIO[20]* /
BS9 mvI/O
A I p/d
U14 LCD21 /
L_GPIO[21]* /
BS10 mvI/O
B I p/u LCD Signal Bus/ BS11。。10 : CHIP_DEB UG_MODE
Select chip debug mode。
0x0: Normal mode
0x1: Debug CPU mode
0x2: Debug CG mode
0x3: Reserved
P15 LCD22 /
L_GPIO[22]* /
BS11 mvI/O
B I p/d
V14 LCD23 /
L_GPIO[23] mvI/O
B I p/d LCD Signal Bus
Note1: The mvI/O voltage of LCD0~23 interface corresponds to VDD M_LCD1 。
L CD interface pinmux table
Name
CCIR 601/656
Serial RGB
CCIR(16 bits)
RGB 16 bits
RGB565
MII(BS)
RMII(BS)
LCD0 YCRG B_D 0 O
CCIR_Y0 O
DR_0 O
C0_0 O
MII_TX_D0 O
RMII_TX_D0 O
LCD1 YCRG B_D 1 O
CCIR_Y1 O
DR_1 O
C0_1 O
MII_TX_D1 O
RMII_TX_D1 O
LCD2 YCRG B_D 2 O
CCIR_Y2 O
DR_2 O
C0_2 O
MII_TX_D2 O
LCD3 YCRG B_D 3 O
CCIR_Y3 O
DR_3 O
C0_3 O
MII_TX_D3 O
LCD4 YCRG B_D 4 O
CCIR_Y4 O
DR_4 O
C0_4 O
MII_TX_EN O
RMII_TX_EN O
LCD5 YCRG B_D 5 O
CCIR_Y5 O
DR_5 O
C1_0 O
MII_TX_ER O
LCD6 YCRG B_D 6 O
CCIR_Y6 O
DR_6 O
C1_1 O
MII_COL I
LCD7 YCRG B_D 7 O
CCIR_Y7 O
DR_7 O
C1_2 O
MII_CRS I
RMII_CRS I
LCD8 YCRG B_C LK O
CCIR_CLK O
DCLK O
DCLK O
MII_TX_CLK I
LCD9 YCRG B_VD O
CCIR_VD O
VD O
VD O
MII_MDC O
MII_MDC O
LCD10 YCRG B_HD O
CCIR_HD O
HD O
HD O
MII_MDIO I/O
MII_MDIO I/O
LCD11
CCIR_DE O
PHY_RST N O
PHY_RST N O
LCD12
CCIR_C0 O
DG_0 O
C1_3 O
MII_RX_D0 I
RMII_RX_D0 I
LCD13
CCIR_C1 O
DG_1 O
C1_4 O
MII_RX_D1 I
RMII_RX_D1 I
LCD14
CCIR_C2 O
DG_2 O
C1_5 O
MII_RX_D2 I
LCD15
CCIR_C3 O
DG_3 O
C2_0 O
MII_RX_D3 I
LCD16
CCIR_C4 O
DG_4 O
C2_1 O
MII_RX_DV I
LCD17
CCIR_C5 O
DG_5 O
C2_2 O
MII_RX_ER I
RMII_RX_ER I
LCD18
CCIR_C6 O
DG_6 O
C2_3 O
MII_RX_CLK I
LCD19
CCIR_C7 O
DG_7 O
C2_4 O
PHY_REFCLK PHY_REFCLK O
LCD20
RMII_REFCLK O
LCD21 SB3_CS
LCD22 SB3_CK
LCD23 SB3_DAT
Note 1*: There are two pins allocated in Peripheral I/O group。 This chip also supports Ethernet MII
interface。
2。7。
PW M and Peripheral I/O ( 2 8)
Pin No。
Name
Ty p e
Reset Descriptions
J16 P_GPIO[0] /
PW M 0 mvI/O
B I p/d
PW M output pin。
Mechanical Shutter control output。
Mic ro -stepping control module 1。
J15 P_GPIO[1]* /
PW M 1 mvI/O
B
I p/d
H15 P_GPIO[2] /
PW M 2 mvI/O
B I p/d
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
K15 P_GPIO[3]* /
PW M 3 mvI/O
B
I p/d
H17 P_GPIO[4] /
PW M 4 mvI/O
B I p/d
PW M output pin。
Mic ro -stepping control module 2。
Serial Peripheral Interface
J17 P_GPIO[5] /
PW M 5 mvI/O
B
I p/d
J18 P_GPIO[6]* /
PW M 6 mvI/O
B I p/d
H18 P_GPIO[7] /
PW M 7 mvI/O
B
I p/d
G18 P_GPIO[8]* /
PW M 8 mvI/O
B I p/d
PWM output pin。
Mic ro -stepping control module 3。
G17 P_GPIO[9] /
PW M 9 mvI/O
B
I p/d
F18 P_GPIO[10] /
PW M 10 mvI/O
B I p/d
H16 P_GPIO[11]* /
PW M 11 mvI/O
B
I p/d
F17 P_GPIO[12] / mvI/O
B I p/d
PW M output pin。
Mic ro -stepping control module 4。
D8 P_ GPIO[13] / mvI/O
B I p/u
B5 P_GPIO[14]* / mvI/O
B I p/u
A5 P_GPIO[15] /
PW M 12 mvI/O
B
I p/u
D7 P_GPIO[16] /
PW M 13 mvI/O
B I p/u
PW M output pin。
Mechanical Shutter control output。
B4 P_GPIO[17]* /
PW M 14 mvI/O
B
I p/u
C5 P_GPIO[18] / mvI/O
B I p/u PW M output pin。
C6 P_GPIO[19]* / mvI/O
A I p/d PW M output pin。
A4 P_GPIO[20] /
REMOTE_RX
/
PICNT3 mvI/O
B I p/u Infrared Remote-control Received Data
Pulse Counter 3 input
A3 P_GPIO[21]* /
FL_TRIG mvI/O
B I p/u Serial Peripheral Interface 2 Data Output
Flash Light Trigger Control
D6 P_GPIO[22]* /
ETH_CLK mvI/O
B I p/u Clock Output for peripheral device。
C4 P_GPIO[23]* /
SP_CLK2 mvI/O
B I p/u Clock Output 2 for peripheral device
D5 P_GPIO[24]* /
PW M15 mvI/O
A I p/u Serial Interface Chip Select 4
D4 P_GPIO[25]* /
SB_CS5 mvI/O
A I p/d Serial Interface Chip Select 5
A6 P_GPIO[26] /
UART_ TX I/O
B O UAR T Tra n smit
B6 P_GPIO[27]* /
UART_RX I/O
B I p/u
UART Receive
Note1: The mvI/O voltage of P_GPIO0~12 interface corresponds to VDD M_PIO。
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Name
PW M
u-stepping
Peripheral
UART
CCIR input
SIE2
Sp ec i al m od e
(RAW 16/CCIR16)
P_GPIO[0] PW M0 O
uSTP1_A O
ME_SHUT0 O
SN2_YC0 I
SN_D4 I
P_GPIO[1] PW M1 O
uSTP1_B O
ME_SHUT1 O
SN2_YC1 I
SN_D5 I
P_GPIO[2] PW M2 O
uSTP1_C O
ME2_SHUT0 O SN2_YC2 I
SN_D6 I
P_GPIO[3] PW M3 O
uSTP1_D O
ME2_SHUT1 O SN2_YC3 I
SN_D7 I
P_GPIO[4] PW M4 O
uSTP2_A O
UART4_T X O
SN2_YC4 I
SN_D8 I
P_GPIO[5] PW M5 O
uSTP2_B O
UART4_RX I
SN2_YC5 I
SN_D9 I
P_GPIO[6] PW M6 O
uSTP2_C O
UART4_RTS O
SN2_YC6 I
SN_D10 I
P_GPIO[7] PW M7 O
uSTP2_D O
UART4_CTS I
SN2_YC7 I
SN_D11(MSB) I
P_GPIO[8] PW M8 O
uSTP3_A O
SPI_CLK O
SN2_MCLK I
SN_D0(LSB) I
P_GPIO[9] PW M9 O
uSTP3_B O
SPI_CS O
SN_D1 I
P_GPIO[10] PW M10 O
uSTP3_C O
SPI_DO IO
SN2_VD I
SN_D2 I
P_GPIO[11] PW M11 O
uSTP3_D O
SPI_DI IO
SN2_HD I
SN_D3 I
P_GPIO[12] O
SN2_PXCLK I
SN_PXCLK I
PW M
u-stepping
Peripheral
UART
I2S / D-Mic
P_GPIO[13]
I2C3_SCL O
P_GPIO[14]
I2C3_SDA I/O
P_GPIO[15] PW M12 O
SP_CLK2 O
SPI_CLK O
UART3_T X O
SB4_CK O
P_GPIO[16] PW M13 O
SPI_CS O
UART3_RX I
SB4_CS O
P_GPIO[17] PW M14 O
SPI_DO IO
UART3_RTS O
SB4_DAT O
P_GPIO[18]
SPI_DI IO
UART3_CTS I
SD_CD I
P_GPIO[19] RT C_CLK O
PICNT3 I
I2S_MCLK O
P_GPIO[20] REMOTE_RX I
SPI3_CLK O
UART2_T X O
I2S_BCLK I/O
P_GPIO[21]
SPI3_CS O
UART2_RX I
I2S_SYNC I/O
P_GPIO[22]
SPI3_DO IO
UART2_RTS O
I2S_SDATAO O
P_GPIO[23]
PICNT2 I
SPI3_DI IO
UART2_CTS I
I2S_SDATAI I
P_GPIO[24] REMOTE_IN I
PICNT
DM_CLK
SD_W P I
P_GPIO[25] PW M15 O
FL_TRIG O
SPI3_RDY
DM_DAT
2。8。
Dedicated I/O ( 2 )
Pin No。
Name
Ty p e
Reset Descriptions
U9 DGPIO0*
/ETH_LNK_LED I/O
A I p/u
T8 DGPIO1* /
ETH_ACT_LED
I/O
A I p/u
2。9。
ADC interface (4)
Pin No。
Name
Ty p e
Reset Descriptions
T12 AD_IN0 AI - General ADC 0 Input with buffer
R12 AD_IN1* AI - General ADC 1 Input with configurable trigger function
T14 AD_IN2* AI - General ADC 2 Input with configurable trigger function
R13 AD_IN3 AI - General ADC 3 Input with buffer
2。10。
Audio Codec(9)
Pin No。
Name
Ty p e
Reset Descriptions
F15 AUD_CAP AI - Internal Supply Voltage decoupling for audio circuit
C18 MIC_BIAS AO - Mic rophone working bias output。
A18 MIC_R_INP AI - Right channel microphone differential input positive side。
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
A17 MIC_R _INN AI - Right channel microphone differential input ne gative side。
B18 MIC_L_INP AI - Left channel microphone differential input positive side。
B17 MIC_L _INN AI - Left channel microphone differential input negative side。
E17 AUD_VMIDX AO - Decoupling for audio codec reference voltage。
D18 LN_R AO - Right channel Line output。 (or headphone out)
E18 LN_L AO - Left channel headphone output。 (or Line out)
2。11。
TV interface (1)
Pin No。
Name
Ty p e
Reset Descriptions
K18 TV_CVBS AO - Video
Data Output
Composite video output 。
2。12。
Ethernet interface ( 4)
Pin No。
Name
Type
Reset Descriptions
U10 ETH_TP AO - Etherner transmit output differential pair
V10 ETH_TN AO - Etherner transmit output differential pair
U11 ETH_RP AI - Etherner receive output differential pair
V11 ETH_RN AI - Etherner receive output differential pair
2。13。
USB device interface ( 3)
Pin No。
Name
Ty p e
Reset Descriptions
R11 VBUS I
5VT I p/d
USB2。0 V
BUS Input 。 This pin is 5V tolerance input
V13 USB 20_DP AI/O - USB 2。0 FS/HS Differential Data Plus (D+)
U13 USB 20_DM AI/O - USB 2。0 FS/HS Differential Data Mi nus (D-)
2。14。
Power (127)
Pin No。
Name
Ty p e Descriptions
F8, G8, G9, G10, G11, G12, G13,
H11, H12, H13, J12,
K7, K8, K12, L8, L11, L12, M11 V
DDC_K(18) P Core Power
F6, F7, N9 VCC_GIO(3) P General 3。3V I/O Pad Power
B2, C3, D3, E2, E4,
F3, F4, G3, G4, H2,
H4, H6, H8, H9,
H10, J4, J7, J8, J9, J10, J11, K4, K9,
K10, K11, L2, L9,
M3, M9 GND
(29) P Digital Ground
K6 VDDC_DRK P Core power for Main DRAM PHY
G6 VDDL_DR P LDO input power for Main DRAM PHY
K3 VDD_DRCLK P Main DRAM Clock power
J6 VDD_DRPIO P Main DRAM I/O Power
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
L6, L7 VDD_DRCIO
(2) P
Main DRAM command and address I/O Power
G7, H7 VDD_DRDIO
(2) P
Main DRAM data I/O Power
J3 VDD_BGDR P Bandgap power for Main DRAM PHY
M7 AV D D_ MP L L P Analog power for Multi -PLL
M8 VDDL_MPLL P LDO input power for Multiple PLL block
N7 GND_MPLL P PLL analog Power
N8 VCC_VBAT P Battery input power for power button controller
N6 VCC _RTC P RTC Power
F12 AV D D C_ H S IK
P Analog core power for HSI PHY
F11 VDDM_HSIO P Multi -level input power for HSI Input
F13 VDD_HSIRX P 2。5V power for HSI receiver
D13 AGND_HSI P Ground for High Speed Interface
F10 VDDM_SN P Multi -level IO power for sensor interface
M12 VCC_SDLI P 3。3V LDO input power for SD Card interface
F9 VDDM_MC P Multi -level IO power for Memory Card
N12, N13 VDDM_LCD(2)
P Multi -level IO power for LCD interface
G16 VDDM_PIO P Multi -level IO power for Peripheral
M10 AV D D_ A D C P Analog 2。5 V power for ADC
L10 AGND_ADC P Ground for ADC
E15 AV C C_ A U D P Analog 3。3V power for Audio Codec
F16, G15 AGND_AUD(2)
P Groun d for Audio Codec
K13 AV D D_ T V P Analog 2。5V power for TV DAC
J13 AGND_TV P Ground for TV DAC
N10 VCC_ETH 3。3V power for ethernet
T10, T11 GND_ETH(2) Ground for Ethernet
N11 AV C C_ U S B P Analog 3。3V power for USB interface
T13 AGND_USB P Ground for US B
E16 TP1_E - Connected 100K Ohm resistor to ground
R14 TP2_S - Connected to ground
R7 TP3_C - Connected to ground
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Package Information
3。
TFBGA-28 8
NT96670
2017/11/06 - 30 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Electrical Characteristics
4。
Absolute Maximum Ratings
Item Symbol Rating Unit
Supply Voltage of 0。9 V core power V
DD C_K -0。3 ~ + 1。2 V
Supply Voltage of 0。9V digital block V
DD C _ DRK -0。3 ~ + 1。2 V
Supply Voltage of 0。9V analog block AV
DD C _ HSI K -0。3 ~ + 1。2 V
Supply Voltage of DRAM I/O V
DD_DRCLK,
V
DD_DRPIO,
V
DD_DRCIO ,
V
DD_DRDIO ,
V
DD _KGD -0。3 ~ + 1。9 V
Supply Voltage of 1。35 / 1。5V digital block
V
DD L _ DR, V
DD L_MPLL -0。3 ~ +1。9 V
Supply Voltage of 2。5V digital block V
DD_ BG DR, V
DD_ HSIRX -0。3 ~ +3。 0 V
Supply Voltage of 2。5V analog block AV
DD_ADC,
AV
DD_ MPL L , AV
DD_ TV -0。3 ~ +3。 0 V
Supply Voltage of 1。5 / 2。5V I/O V
D D M_H S IO -0。3 ~ +3。 0 V
Supply Voltage of multi -level I/O V
DDM_MC,
V
DDM_SN
,
V
D DM_PIO , V
DD M _ LCD -0。3 ~ +3。8 V
Supply Voltage of 3。3V digital I/O V
CC_VBAT
, V
CC_RTC
,
V
CC_GIO, V
CC_SDLI,
V
CC_ETH -
0。3 ~ +3。8 V
Supply Voltage of 3。3V analog block AV
CC_AUD,
AV
CC_ USB -0。3 ~ +3。8 V
Input/Output Voltage I/O -0。3 ~ V
DD_IO +0。3 V
Input Voltage (5V Tolerant) I/O
5VT -0。3 ~ +5。8 V
Operating Ambient Temperature T
OPR -20 ~ 70
0
C
Junction Operating Temperature T
J -40~125
0
C
Storage Temperature T
STG -55 ~ 125
0
C
*
Commen t
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to this
device。 These are stress ratings only。 Functional operation of this device at these or any other
conditions above those indicated in the operational sections of this specification is not implied or
intended。 Exposure to the absolute maximum rating conditions for extended periods may affect device
reliability。
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
5。
ESD performance
Model Standard Classification Note
Human Body Mode(HBM) JEDEC EIA/ JESD22 -A1 14-F Class : 2 2KV~4KV
Machine Mode(MM) JEDEC EIA/JESD22 -A11 5-C
Class : B 200~400V
CDM Mode(CDM) JEDEC Standard JESD22 -C101 -C Class : III 500~1KV
6。
Latch-up Immunity
Model Standard Classification Note
Latch up JEDEC Standard EIA/ JESD -78A
Class : I
Level : A ±
200m A
7。
Recommended Operating Conditions
Symbol
Parameter
Min。
Ty p 。
Max。
Unit
Conditions
V
DDC_K Core Logic Operating
Vo l ta ge 0。81
0。9 0。99 V
V
CC_GIO General
I/O Interface
Operating Voltage 3。0
3。3 3。6 V
V
DDC_DRK
Core Logic of DRAM
PHY Operating Voltage
0。81 0。9 0。99 V
V
DDL_DR
LDO of DRAM PHY
Operating Voltage 1。283
1。5 1。65 V
V
DD_DRCLK
DRAM clock Operating
Vo l ta ge 1。425
1。5 1。575
V DDR3 /DDR2L DRAM
1。283 1。35 1。45 V DDR3L DRAM
V
DD_MDR PIO
V
DD_MDRC IO
V
DD_ MDRD IO DRAM PHY I/O
Operating Voltage 1。425
1。5 1。575
V DDR3 /DDR2L DRAM
1。283 1。35 1。45 V DDR3L DRAM
V
DD_KGD
KGD DRAM
Operating
Vo l ta ge 1。425
1。5 1。575
V DDR3/DDR2L DRAM
1。283 1。35 1。45 V DDR3L DRAM
V
DD_BGDR
Bandgap of DRAM PHY
Operating Voltage 2。25
2。5 2。75 V
AV
DD_MPLL
MPLL Operating
Vo l t age 2。25
2。5 2。75 V
V
DDL_MPLL
LDO of MPLL Operating
Vo l ta ge 1。283
1。5 1。65 V
V
CC_VBAT
Power Controller
Operating Voltage 2。2
- 3。6 V
V
CC _RTC O RTC Operating Voltage 2。5 - 3。3 V
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
V
CC_RTC M
RTC Maintenance
Vo l ta ge 2。0
- 3。3 V
AV
DDC_HSIK
Core Logic of High
Speed Interf ace
Operating Voltage 0。
85 0。9 0。99 V
V
DDM_H S IO
Input of High Speed
Interface Operating
Vo l ta ge 1。62
1。8 2。75 V 1。8V~2。5V
V
DD_HSIRX
Receiver of High Speed
Interface Operating
Vo l ta ge 2。25
2。5 2。75 V
V
DDM_SN
I/O
of Sensor Interface
O perating Voltage 1。62
1。8 3。6 V 1。8V~3。3V
V
CC_SDLI LDO of SD Card
Interface Operating
Vo l ta ge 3。0
3。3 3。6 V
V
DDM_MC
I/O of Memory Card
Interface Operating
Vo l ta ge 1。62
3。3 3。6 V 1。8V~3。3V
V
DDM_LCD
I/O of LCD Interface
Operating Voltage 1。62
3。3 3。6 V 1。8V~3。3V
V
DDM_PIO
I/O of Peripheral
Operating Voltage 1。62
3。3 3。6 V 1。8V~3。3V
AV
DD_ ADC ADC Operating Voltage 2。25 2。5 2。75 V
AV
CC_AUD Audio Codec Operating
Vo l ta ge 3。
1 3。3 3。6 V
V
CC_ET H
Ethernet
Operating
Vo l ta ge 3。0
3。3 3。6 V
AV
DD_TV
TV DAC Opera
ting
Vo l ta ge 2。25
2。5 2。75 V
AV
CC_USB USB Interface
Operating Voltage 3。0
3。3 3。6 V
8。
AC/DC Characteristics
8。1。
Power on Sequence
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
Power on sequence and Reset
T
RST RESET# sustained time 1 - - ms
After power b eing stable
T
PW R Core power prior to I/O
power time 1
- - ms
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
POWER-ON SQUENCE
V
CCK
V DD _DRAM
V DD _IO
RESET #
t1
GND
GND
3。0 V
GNDt PWR >1ms
GND
t RST = 1 ms
GNDVDD _IO , RESET #
VDD_DRAM
V CCK
VOLTAGE TIME
t2 > 0ms
Note : Even t
1 ≧0 ms or t
1 <0 ms is acceptable , but it is necessary to make sure t
2 >0 ms 。
NT96670
2017/11/06 - 34 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
POWER-OFF SEQUENCE
V
CCK
V DD _DRAM
V DD _IO
RESET
#
GND
GND
GNDt6
>0ms
GND
GNDVDD _DRAM
V CCK
VOLTAGE TIME
t5
>0ms
t4
>0ms
Note :
Novatek recommend s that t
4 >0 ms, t
5 >0 ms, and t
6 >0 ms for a stable system application。 But th ey
are not the required restriction s for Novatek ’s DSP。
NT96670
2017/11/06 - 35 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
8。2。
General I/O
(V
DDK =0。9 V, Te m p = 2 5
0
C)
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
3。3V I/O (I/O
ABCDE ) General characteristic
V
DD_ IO IO power supply 3。0 3。3 3。6 V
V
IH Input high voltage 2。0 - - V
V
IL Input low voltage - - 0。8 V
V
T+
Schmitt trigger high
threshold 1。60
1。7 1。95 V
V
T-
Schmitt trigger low
threshold 1。05
1。25 1。4 V
V
HYST Hysteresis - 0。52 - V
V
OH Output high voltage V
DD_IO
-0。4 -
- V
V
OL Output low voltage - - 0。4 V
I
LI Input leakage current -10 - +10 uA
I
LO Output leakage current -10 - +10 uA
R
PU Pull -up resistor 50 80 130
k
R
PD Pull -down resistor 50 90 160
k
3。3V I/O
A Output
Capability
I
OH Output high driving
current 6
- - mA
Level setting 0
16 - - mA
Level setting 1
I
OL Output low driving current
6 - - mA
Level setting 0
16 - - mA
Level setting 1
3。3V I/O
B Output
Capability
I
OH Output high driving
current 4
- - mA
Level setting 0
10 - - mA
Level setting 1
I
OL Output low driving current
4 - - mA
Level setting 0
10 - - mA
Level setting 1
3。3V I/O
C Output
Capability
I
OH Output high driving
current 16
- - mA
Level setting 0
I
OL Output low driving current
16 - - mA
Level setting 0
3。3V I/O
D Output
Capability
I
OH Output high driving
current 8
- - mA
Level setting 0
I
OL Output low driving current
8 - - mA
Level setting 0
3。3V I/O
E Output
Capability
I
OH
Output high driving
current 4
- - mA
Level setting 0
10 - - mA
Level setting 1
I
OL Output low driving current
4 - - mA
Level setting 0
10 - - mA
Level setting 1
3。3V I/O
SD Output
Capability
R
PU Pull -up resistor 10 20 30
k
NT96670
2017/11/06 - 36 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
R
PD Pull -down resist or 15 25 40
k
I
OH Output high driving
current 3
- - mA
Level setting 0
6 - - mA
Level setting 1
9 - - mA
Level setting 2
12 - - mA
Level setting 3
15 - - mA
Level setting 4
18 - - mA
Level setting 5
21 - - mA
Level setting 6
24 - - mA
Level setting 7
I
OL Output low driving current
3 - - mA
Level setting 0
6 - - mA
Level setting 1
9 - - mA
Level setting 2
12 - - mA
Level setting 3
15 - - mA
Level setting 4
18 - - mA
Level setting 5
21 - - mA
Level setting 6
24 - - mA
Level setting 7
2。5V I/O (I/O
ABCDE ) General characteristic
V
DD_IO IO power supply 2。25 2。5 2。75 V
V
IH Input high voltage 1。7 - - V
V
IL Input low voltage - - 0。7 V
V
T+
Schmitt trigger high
threshold 1。25
1。4 1。55 V
V
T-
Schmitt trigger low
thr eshold 0。8
0。95 1。1 V
V
HYST Hysteresis - 0。45 - V
V
OH Output high voltage V
DD_IO
-0。4 -
- V
V
OL Output low voltage - - 0。4 V
I
LI Input leakage current -10 - +10 uA
I
LO Output leakage current -10 - +10 uA
R
PU Pull -up resistor 60 100 170
k
R
PD Pull -down resistor 60 11 0 220
k
2。5V I/O
A Output
Capability
I
OH Output high driving
current 4。5
- - mA
Level setting 0
12 - - mA
Level setting 1
I
OL Output low driving current
4。5 - - mA
Level setting 0
12 - - mA
Level setting 1
2。5V I/O
B Output
Capability
I
OH Output high driving
current 3
- - mA
Level setting 0
7。5 - - mA
Level setting 1
I
OL Output low driving current
3 - - mA
Level setting 0
7。5 - - mA
Level setting 1
2。5V I/O
C Output
Capability
I
OH Output high driving 12 - - mA
Level setting 0
NT96670
2017/11/06 - 37 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
current
I
OL Output low driving current
12 - - mA
Level setting 0
2。5V I/O
D Output
Capability
I
OH Output high driving
current 6
- - mA
Level setting 0
I
OL Output low driving current
6 - - mA
Level setting 0
2。5V I/O
E Output
Capability
I
OH Output high driving
current 3
- - mA
Level setting 0
7。5 - - mA
Level setting 1
I
OL Output low driving current
3 - - mA
Level setting 0
7。5 - - mA
Level setting 1
1。8V I/O (I/O
ABCDE ) General characteristic
V
DD_IO IO power supply 1。62 1。8 1。98 V
V
IH Input high voltage V
DD_IO
*0。7 -
- V
V
IL Input low voltage - - V
DD_IO
*0。3 V
V
T+
Schmitt trigger high
threshold 0。9
1。1 1。25 V
V
T-
Schmitt trigger low
threshold 0。55
0。7 0。8 V
V
HYST Hysteresis - 0。4 - V
V
OH Output high voltage V
DD_IO
-0。4 -
- V
V
OL Output low voltage - - 0。4 V
I
LI Input leakage current -10 - +10 uA
I
LO Output leakage current -10 - +10 uA
R
PU Pull -up resistor 100 175 300
k
R
PD Pull -down resistor 100 200 420
k
1。8V I/O
A Output
Capability
I
OH Output high driving
c urrent 3
- - mA
Level setting 0
8 - - mA
Level setting 1
I
OL Output low driving current
3 - - mA
Level setting 0
8 - - mA
Level setting 1
1。8V I/O
B Output
Capability
I
OH Output high driving
current 2
- - mA
Level setting 0
5 - - mA
Level setting 1
I
OL Output low driving current
2 - - mA
Level setting 0
5 - - mA
Level setting 1
1。8V I/O
C Output
Capability
I
OH Output high driving
current 8
- - mA
Level setting 0
I
OL Output low driving current
8 - - mA
Level setting 0
1。8V I/O
D Output
Capability
I
OH Output high driving
current 4
- - mA
Level setting 0
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
I
OL Output low driving current
4 - - mA
Level setting 0
1。8V I/O
E Output
Capability
I
OH Output high driving
current 2
- - mA
Level setting 0
5 - - mA
Level setting 1
I
OL Output low driv ing current
2 - - mA
Level setting 0
5 - - mA
Level setting 1
1。8V I/O
SD Output
Capability
R
PU Pull -up resistor 30 45 60
k
R
PD Pull -down resistor 30 50 80
k
I
OH Output high driving
current 1。5
- - mA
Level setting 0
3 - - mA
Level setting 1
4。5 - - mA
Level setting 2
6 - - mA
Level setting 3
7。5 - - mA
Level setting 4
9 - - mA
Level setting 5
10。5 - - mA
Level setting 6
12 - - mA
Level setting 7
I
OL Output low driving current
1。5 - - mA
Level setting 0
3 - - mA
Level setting 1
4。5 - - mA
Level setting 2
6 - - mA
Level setting 3
7。5 - - mA
Level setting 4
9 - - mA
Level setting 5
10。5 - - mA
Level setting 6
12 - - mA
Level setting 7
8。3。
Specif ic function I/O(RTC, Reset, LVD and PBC)
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
RTC
T
START-UP
RTC 32768Hz crystal start
up time -
250 - ms
V
DD_RTC = 3 V
I
RT C Operating current of RTC
- - 2 uA
V
DD_RTC = 2。5V
V
DD_RTCO Operating voltage of RTC 2。5 - 3。6 V V
DD_BAT >= 2。2V
V
DD_RTCM Maintenance voltage of
RTC 2
- 3。6 V no V
DD_BAT
RESET# & Low Voltage Detector
R PU_RST Pull-Up Resistor of
RESET# -
113 - KΩ
VDD_IO=3。3V
R PD_RST Pull-Down R esistor of
RESET# -
800 - Ω VDD_IO=3。3V
V
LV D _ D E T + LV D Lo g i c 1 Det e ct Le ve l - 2。6 2。7 V
V
LV D _ D E T - LV D Lo g i c 0 Det e ct Le ve l 2。25 2。45 - V
V
T+_RESET Schmitt Trigger Positive
Going Threshold (RESET)
- 2。35 2。75 V
V
T - _RESET Schmitt Trigger Negative 1。25 1。75 - V
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2017/11/06 - 39 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Going Threshold (RESET)
Power Button Controller
V
T+ Schmitt Trigger Positive
Going Threshold
(PWR_SW1,PWR_SW2,
PWR_SW3,PWR_SW4) -
1。6 1。8 V V
DD_RTC = 3。0V
V
T-
Schmitt Trigger Negative
Going Threshold
(PWR_SW1,PWR_SW2,
PWR_SW3,PWR_SW4) 1
1。2 - V V
DD_RTC = 3。0V
V PFD+ PFD Positive Going
Threshold Voltage
(Core power) -
0。75 0。8 V
V PFD-
PFD Negative Going
Threshold Voltage
(Core power) 0。
65 0。7 - V
I
SW 1-pd
Pull
-Down Current
(PWR_SW1) -
10 - uA
V
DD_RTC = 3。0V
I
SW 2-pu
Pull
-Up Current
(PWR_SW2) -
10 - uA
V
DD_RTC = 3。0V
I
SW 3-pd
Pull
-Down Current
(PWR_SW3) -
3 - uA
V
DD_RTC = 3。0V
I
SW 4-pd
Pull
-Down Current
(PWR_SW4) -
1 - uA
V
DD_RTC = 3。0V
R
OH Resistor of PWR_EN
Output High 110 0
1300
1500 Ω V
OH
=2。9 V, V
DD_VBAT =3。3 V
R
OL Resistor of PWR_EN
Output Low 180
250 320 Ω V
OL
=0。4 V, V
DD_VBAT =3。3 V
V
OH PWR_EN Output High
Vo l ta ge V
DD_VBAT
- 0。2 -
- V @ I
OH
= 100uA
V
OL PWR_EN Output Low
Vo l ta ge -
- 0。1 V @ I
OL
= -100uA
8。4。
DDR3 / DDR3L Interfance
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
DC specificatio n
V
REF DDR PHY
I/O Reference
Vo l ta ge 0。49*
V
DD_DR - 0。51*
V
DD_DR V
DDR3 Single-Ended Output logic level
V
OH(DC) DC Output High (Logic 1)
Voltage V
REF
+0。100 - V
DD_DR V
V
OL(DC) DC
Output Low (Logic 0)
Voltage V
SS - V
REF
-0。100
V
V
OH(AC) A
C Output Hi gh (Logic 1)
Voltage V
REF
+0。15 - Note1
V
V
OL(AC) A
C Output Low (Logic 0)
Voltage Note1
- V
REF
-0。15
V
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
DDR3L Single-Ended Output logic level
V
OH(DC) DC Output High (Logic 1)
Voltage V
REF
+0。09 - V
DD_DR V
V
OL(DC) DC
Output Low (Logic 0)
Voltage V
SS - V
REF
-0。09
V
V
OH(AC) A
C Output High (Logic 1)
Voltage V
REF
+0。135 - Note1
V
V
OL(AC) A
C Output Low (Logic 0)
Voltage Note1
- V
REF
-0。135
V
DDR3 Differential Output logic level
V
OH(Diff) Differential output high
voltage 0。200
- Note2
V
V
OL(Diff) Di
fferential output low
voltage Note2
- -0。200
V
V
OHDiff(AC) Differential output high AC
voltage 2 *
(V
OH(AC)
- V
REF ) - Note2
V
V
OLDiff(AC) Differential input low AC
voltage Note2
- 2 *
(V
REF
- V
OL(AC) ) V
V
OX(DQS) Differential output cross
point relati ve to V
DD_DR
/2
for DQS , DQS # -
150 - 150 mV
V
OX(CK) Differential output cross
point relative t o V
DD_DR
/2
for CK, CK# -
175 - 175 mV
DDR3L Differential Output logic level
V
OH(Diff) Differential output high
voltage 0。180
- Note2
V
V
OL(Diff) Differentia
l output low
voltage Note2
- -0。180
V
V
OHDiff(AC) Differential output high AC
voltage 2 *
(V
OH(AC)
- V
REF ) - Note2
V
V
OLDiff(AC) Differential input low AC
voltage Note2
- 2 *
(V
REF
- V
OL(AC) ) V
V
OX(DQS) Differential output cross
point relative t o V
DD_DR
/2
for DQS , DQS # -
150 - 150 mV
V
OX(CK) Differential output cross
point relative t o V
DD_DR
/2
for CK, CK# -
150 - 150 mV
DDR3 AC spe c if ic a tion
FCLK
DDR3 Clock Frequency 400 - 800 Mhz
tCH
clock high pulse width 0。43 - - t
CK
tCL
clock low pulse width 0。43 - - t
CK
NT96670
2017/11/06 - 41 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
t
DQSH DQS,DQS# differential
optput high time 0。45
-
0。55 t
CK
t
DQSL DQS,DQS# differential
optput low time 0。45
-
0。55 t
CK
t
DQSS DQS,DQS# rising edge
output access time from
rising CK,CK# -
0。25
0。25
t
CK
Note
1。 Refer to JESD79 -3F “Overs hoot and Undershoot Specifications”
2。 These values are not defined; however, the single -ended signals CK, CK#, DQS,
DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the respective limits (V IH(dc)
max, VIL(dc)min) for single -ended signals as well as the limit ations for overshoot and
undershoot。 Refer to JESD79-3F “Overshoot and Undershoot Specifications”
8。5。
High speed serial interface(MIPI CSI, LVDS, HiSPi)
Symbol Parameter
Min。
Ty p 。
Max。 Unit Conditions
Input Impedance
Z
ID Imp
edance of Differential
Te r m i n a t o r 80
100 125 Ohm
(check resistor’s accuracy)
LV DS / Hi SP i (S ub-LV D S / H i V C M)
HS Receiver DC Specifications
V
CMRX(DC) Common-mode voltage
HS receive mode 600
900 1200
mV
VIDTH
Differential input high
threshold -
- 70 mV
(“Z ” : 25mV)
VIDTL
Differential input
low
threshold -
70 - - mV
(“Z ” : -25mV)
VIHHS
Single
-ended input high
voltage -
- 1500
mV (1200+300)
VILHS
Single
-ended input low
voltage 400
- - mV
HiSPi(SLVS) HS Receiv er DC Specifications
V
CMRX(DC) Common-mode voltage
HS receive mode 150
200 250 mV
VIDTH
Differential input high
threshold -
- 70 mV
(“Z ” : 25mV)
VIDTL
Differential input low
threshold -
70 - - mV
(“Z ” : -25mV)
VIHHS
Single
-ended input high
voltage -
- 490 mV
(360+130))
VILHS
Single
-ended input low
voltage -
10 - - mV
(120-130)
MIPI
HS Receiv er DC Specifications
V
CMRX(DC) Common-mode voltage
HS receive mode 70
- 330 mV
Note 1,2
VIDTH
Differential input high
threshold -
- 70 mV
VIDTL
Differential input low
threshold -
70 - - mV
NT96670
2017/11/06 - 42 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
VIHHS
Single
-ended input high
voltage -
- 460 mV
Note 1
VILHS
Single
-ended input low
voltage -
40 - - mV
Note 1
Note
1。 Excluding possible additional RF interface of 100mV peak sine wave beyond 450MHz。
2。 This table value includes a ground difference of 50mV between the transmitter and the
receiver, the static common-mode level tolerance and variation below 450MHz。
MIPI LP Receiv er DC specifications
V
IH Logic 1 input voltage 880 - - mV
V
IL Logic 0 input voltage, not
in ULP State -
- 500 mV
V
HYST Input Hysteresis 25 - - mV
General Purpose Input DC specifications
V
T+ Schmitt Trigger Positive
Going Threshold -
- - 2。0 V V
DDM_HSIO = 2。5V
V
T-
Schmitt Trigger Negative
Going Threshold 0。9
- - V V
DDM_HSIO = 2。5V
V
HYST Input Hysteresis 0。25 - - V V
DDM_HSIO = 2。5V
RPD Pull Down Resistance - 160K - Ohm
VDDM_HSIO = 2。5V
V
T+ Schmitt Trigger Positive
Going Threshold -
- 1。2 V V
DDM_HSIO
= 1。8V
V
T-
Schmitt Trigger Negative
Going Threshold 0。6
- - V V
DDM_HSIO
= 1。8V
V
HYST Input Hysteresis 0。2 - - V V
DDM_HSIO = 1。8V
R
P D Pull Down Resistance - 290K - Ohm
V
DDM_HSIO = 1。8V
LV DS / Hi SP i Receiver AC Specifications
F
CLK - - 750 MHz
C
CM Common
-mode
termination -
10 - pF
(5pF option)
MIPI HS Receiv er AC specifications
F
CLK 40 - 750 MHz
ΔV
CMRX_
HF Common
-mode
interference beyond
450MHz -
- 100 mV
Note 2
ΔV
CMRX_
LF Com
mon-mode
interference
50MHz -450MHz -
50 - 50 mV
Note 1,4
C
CM Common
-mode
termination -
10 60 pF
Note 3 (5pF option)
Note
1。 Excluding ‘static’ ground shift of 50mV
2。 ΔV
CMRX(HF) is the peak amplitude of a sine wave superimposed on the receiver inputs。
3。 For high er bit rates a 14pF capacitor will be needed to meet the common -mode return
loss specification。
4。 Vo l ta ge d i ff e re n ce co mpa r ed to D C a v e ra ge c o mmo n -mode potential。
MIPI LP Receiv er AC specifications
e
SPIKE Input pulse rejection - - 300 Vps
Note 1,2,4
T
MIN - RX Minimum pulse width 20 - - nS
Note 4
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
response
V
INT
Peak interference
amplitude -
- 200 mV
f
INT Interference frequency 450 - - MHz
Note
1。 Time -voltage integration of a spike above V
IL when being in LP -0 state or below V
IH
when being in LP-1 state。
2。 An impulse less than this will not change the receiver state。
3。 In addition to the required glitch rejection, implements shall ensure rejection of known
RF-interferences。
4。 An input pulse greater than this shall toggle the output。
8。6。
High speed serial interface (SLVS -EC )
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
Common Parameters
BER Bit Error Rate - - 10
- 10
UI Unit Interval
- 434 - pS
2304Mbps
Input Impedance
Z
DMRX Imp
edance of Differential
Te r m i n a t o r 80
100 110 Ohm
(check resistor’s accuracy)
DC Specifications
V
CMRX(DC) Receiver Common-m ode
Input V oltage 25
300 mV
VDMRX(AC)
Receiver Differential Input
V oltage -
65 - 285 mV
Timin g Sp e cif ica t ion
V
CMRX(DC) Common-mode voltage
HS receive mode 150
200 250 mV
VILHS
Single
-ended input low
voltage -
10 - - mV
(120-130)
General Parameters
Symbol Parameter
Min。
Ty p 。
Max。
Unit
Conditions
V
DIF_RX Receiver Input Differential
Peak -Peak Voltage 65
- 285 mV
Vcm_RX
Receiver Input Common
Mode Voltage 25
- 300 mV
RDIF_RX
Receiver Input Differential
Resi stance 80
- 11 0 ohm
Timing Parameters
Symbol Parameter
Min。
Ty p 。
Max。
Unit
Conditions
T
HLW _RX Reeciver Input High/Low
Width 0。2
- - UI
LPJ_RX Receiver Input Long
periodic Jitter -
- 0。3 UI Periodic Jitter Frequency
≦
20MHz
SPJ_RReceiver Input Short - - 0。15 UI Periodic Jitter Frequency
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
X Periodic Jiffer >20MHz
LT J_ RX Receiver Input Long term
To t a l J i t t e r -
- 0。5 UI LTJ_RX=LPJ_RX+Random
Jitter Component(BER ≦
10
-10
) + ISI on Interconnect
(ISI : Inter Symbol
Interferenc e)
STJ_RX Receiver Input Short term
To t a l J i t t e r -
- 0。3 UI STJ_RX=SPJ_RX
+Random Jitter
component(BER ≦10
-10
,
Filtered off component ≦
20MHz)+ISI on
Interconnect。
TLSKEW_RX
Receiver Input Skew
between lanes(up to 8
lanes) -
- 6
SI In case of TX Internal
Da ta-Bus Width:10 -bit
10 In case of TX Internal
Data -Bus Width:20 -bit
Common Characteristics
Common Parameters
Symbol Parameter
Min。
Ty p 。
Max。
Unit
Conditions
NT96670
2017/11/06 - 45 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
BER Bit Error Rate - - 10
- 10
UI_2304M Unit Interval (2304Mbps)
434 ps
Reference Clock Parameters
Symbol Parameter
Min。
Ty p 。
Max。
Unit
Conditions
F
REF72M Reference Clock Frequence
(72MHz)
72 MHz Reference Clock for Sensor
Duty
_REF Reference Clock Duty Cycle 40 50 60 %
PN100K Reference Clock Phase
Noise at 10 0KHz -
- -135 dBc/Hz
PN1M Reference Clock Phase
Noise at 1M -
- -140 dBc/Hz
F
ERR Reference Clock Frequency
Error -
300 - 300 ppm
8。7。
ADC
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
RES ADC Effective Resolution
- 8 - Bits
9 bits SAR ADC structure
≦ 12 5KSPS
V
I N Input signal level 0 - V
DD - ADC V
INL Integral nonlinearity -2 - +2 LSB
DNL Differential nonlinearity -1 - +1 LSB
C
IN
Input capacitance of
channel -
20 - pF
C
IN -buffer
Input capacitance of
buffer -
1 - pF
8。8。
Audio Codec
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
Mic rophone
V
MIC_BIAS Mic Bias Output Level -
2。0 - V Setting 0
- 2。5 - V Setting 1
V
IN Input Full Scale Level - 2。65 - Vpp
0dB gain
SNR Signal to Noise Ratio - 85 - dBA
0dB gain, A-weighting。。
THD+N To t a l H a r m o n i c D i stortion
Plus Noise Ratio -
-80 - dBA
0dB gain, A-weighting。
R
IN Input Resistance -
2。38 - KΩ
PGA gain set to +25。5 dB
- 24 - KΩ
PGA gain set to 0 dB
- 44。2 - KΩ
PGA gain set to -21 dB
G
PGA Programable Gain
Amplifier Range -
21 - +25。5
dB 32 steps
G
ST EP Programable Gain
Amplifier Step Size -
1。5 - dB
G
Boost Boost Gain - 20 - dB
0/10/20/30 dB
Headphone or Line Out @1K Load
NT96670
2017/11/06 - 46 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
SNR Signal to Noise Ratio - 84 - dBA
THD+N To t a l H a r m o n i c D i s t o r t i o n
Plus Noise Ratio -
-80 - dBA
G
PGA Programable Gain
A mplifier Range -
31。6
- +6 dB
G
ST EP Programable Gain
Amplifier Step Size -
1。2 - dB
C
R Crosstalk Ratio - -80 - dB
8。9。
TV encoder
(R
LOAD = 37。5 Ω, Conversion rate = 27M Hz)
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
RES Video DAC
Effective
Resolution -
10 - bits
10-Bits I -Steering DAC structure
INL Integral Nonlinearity, INL -2 - +2 LSB
DNL Differential Nonlinearity,
DNL -
1 +1 LSB
I
CODE Output Current
-DAC
Code 1023 (Iout FS) -
34 - mA
R
load = 37。5 Ohm
V
CODE Out Voltage
-DAC Code
1023 -
1。275
- V R
load = 37。5 Ohm
VLE Video Level Error -5 - +5 %
V
OC Output Compliance
Range 0
- 1。4 V
F
CLK Conversion rate - 27 - MHz
8。10。
USB 2。0(Hi gh-Sp ee d/ F u l l -Sp ee d )
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
High Speed DC Specifications
Input Levels (differential receiver)
V
HSDIFF High speed differential
input sensitivity 300
- - mV
|V
I(DP) -V
I(D M) | measured at the
connection as application circuit
V
HSCM High speed data signaling
common mode voltage
range -
50 - 500 mV
V
HSSQ High speed squelch
detection threshold -
- 100 mV
squelch detected
150 - - mV
no squelch detected
V
HSDSC High speed disconnection
detection threshold 625
- - mV
disconnection detected
- - 525 mV
disconnection not detected
Output Levels
V
HSOI High speed idle level
output voltage
(differential) -
10 - 10 mV
V
HSOL High speed low level
output voltage -
10 - 10 mV
NT96670
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With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
(differential)
V
HSOH High speed high level
output voltage
(differential) -
360 - 400 mV
V
CHRPJ Chirp
-J output voltage
(differential) 700
- 110 0 mV
V
CHIRPK Chirp-K output voltage
(differential) -
900 - -500 mV
Resistance
R
DRV Driver output impedance 3
6 9 Ω equivalent resistance used as
internal chip only
40。5 45 49。5 Ω overall resistance including
external resistor
Te r m i n a t i o n
V
TERM Te r m i n a t i o n v o l t a g e f o r
pull -up resistor on pin
RPU 3。0
- 3。6 V
Full Speed DC Specifications
Input Levels (differential receiver)
V
DI Differential input
sensitivi ty 0。2
- - V |V
I(DP) -V
I(D M) |
V
CM Differential common mode
voltage 0。8
- 2。5 V
Input Levels (single-ended receivers)
V
SE Single ended receiver
threshold 0。8
- 2。0 V
Output Levels
V
OL Low -level output voltage 0 - 0。3 V
V
OH High -level output voltage 2。8 - 3。6 V
High Speed AC Specifications
Driver Characteristics
T
HSD R AT E High speed TX data rate 479。76
- 480。24
Mbps
T
HSRD R AT E High speed RX data rate 479。76
- 480。24
Mbps
t
HSR High speed differential
rise time 500
- - ps
t
HSF High speed differe
ntial fall
time 500
- - ps
Driving timing
Driver waveform
requirement see eye pattern of template 1
Follow template1 described in
USB2。0 spec
Receiver timing
Data source jitter and
receiver jitter tolerance see eye pattern of template 4
Follow template 4 described in
USB2。0 spec
Full Speed AC Specifications
Driver Characteristics
T
FSD R AT E Full speed TX data rate 11。 99 4
- 12。006
Mbps
T
FSRD R AT E Full speed RX data rate 11。 97
- 12。03
Mbps
NT96670
2017/11/06 - 48 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
t
FR Rise time 4 - 20 ns CL=50pF; 10 to 90% of
|V
OH -V
OL |
t
FF
Fall time 4 - 20 ns CL=50pF; 90 to 10% of
|V
OH -V
OL |
t
FRMA Differential rise/fall time
matching (t
FR /t
FF ) 90
- 110 % Excluding the first transition
from idle mode
V
CRS Output signal crossover
voltage 1。3
- 2。0 V Excluding the first transition
from idle mode
Driving timing
VI, FSE0, OE to DP, DN
propagation delay -
- 15 ns for detailed description of VI,
FSE0 and OE, please refer to
USB1。1 spec
T
FDEOP
Source jitter for differential
transition to SE0 transition -2 - 5 ns
T
JR1 Receiver jitter -18。5
- 18。5 ns To n e x t t r a n s i t i o n
T
JR2 Receiver jitter -9 - 9 ns For paired transition
T
FEOPT
Source SE0 interval of
EOP 160
- 175 ns
T
FEOPR
Receiver SE0 interval of
EOP 82
- - ns
T
FST
Width of SE0 interval
during differential
transition -
- 14 ns
Receiver timing
t
PLH(RCV)
t
PHL(RCV) Receiver propagation
delay (DP; DM to RCV) -
- 15 ns for detailed description of RCV,
please refer to USB1。1 spec
t
PLH(single)
t
PHL(single) Receiver propagation
delay (DP; DM to VOP,
VON) -
- 15 ns
NT96670
2017/11/06 - 49 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Differential
Data Lines
10% 90%
10% 90%
FRt
FFt
Full speed Data Signal Rise and Fall time
TxD+
TxD-
SR
SR LC
LCFull-speed
Vbus
D+
D -
GND
Tes t Su p p l y Vo l t a g e
。
143
Ohm 143
Ohm +-
To 50 Ohm Inputs of a High
speed Differential OscilloscopeUSB
Connector
nearest Device
Under Test 15。8 Ohm
15。8 Ohm
Differential
Data Lines
10% 90%
10% 90%
HSR
t
HSF
t
High speed Data Signal Rise and Fall time
NT96670
2017/11/06 - 50 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
8。11。
USB Charging Port Detect
USB charging port detect
Symbol Parameter
Min。
Ty p 。
Max。
Unit Conditions
V
D AT _ R E F Data Detect Voltage 0。25 - 0。4 V
V
D M_ SRC D- Source Voltage 0。5 - 0。7 V
V
D P_SRC D+ Source Voltage 0。5 - 0。7 V
V
LGC Logic Threshold 0。8 - 2。0 V
V
LGC_HI Logic High 2。0 - 3。6 V
V
LGC_LOW Logic Low 0 - 0。8 V
I
DM_SINK D- Sink Current 25 - 175 uA
I
DP_SINK D+ Sink Current 25 - 175 uA
I
DP_SRC Data Contact Detect
Current Source 7
- 13 uA
R
DM_DW N D- Pull -down resistance 14。25
- 24。8 kΩ
Differential
Data Lines
Full speed Output Signal Crossover Voltage
TxD+
TxD-
SR
SR LC
LCFull-speed
CRS
V
CRS
V
NT96670
2017/11/06 - 51 - Version 0。 3
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of
merc hantability, fitness for a partic ular purpose, non -infringement, or assumes any legal l iability or respons ibility for the accuracy,
completeness, or usefulness of any such information。
Important Notice
NT96670 is not specif ically designed and marketed to and directly and knowingly sold or used
for any
(i) military products or proliferation application (including but not limited to missiles, n uclear,
chemical and biological weapons); or
(ii) commercial space products or applications that are controlled under the U。S。 Munitions List (USML);
or
(iii) medical appliances; and
NT96670 shall be not directly and knowingly shipped to any co untries subject to “ embargo ” under
U。S。 or other applicable laws。